KEY WORDS: nonvolatile, memory, hot-carrier injection, tunneling, reliability, retention, memory disturbs, EPROM, Flash EEPROM
Memory can be split into two main categories: volatile and nonvolatile. Volatile memory loses any data as soon as the system is turned off; it requires constant power to remain viable. Most types of random access memory (RAM) fall into this category. Nonvolatile memory does not lose its data when the system or device is turned off. A nonvolatile memory (NVM) device is a MOS transistor that has a source, a drain, an access or a control gate, and a floating gate. It is structurally different from a standard MOSFET in its floating gate, which is electrically isolated, or "floating". Nonvolatile memories are subdivided into two main classes: floating gate and charge-trapping. Kahng and Sze proposed the first floating gate device in 1967 . In this memory, electrons were transferred from the floating gate to the substrate by tunneling through a 3 nm thin silicon dioxide (SiO2) layer. Tunneling is the process by which an NVM can be either erased or programmed and is usually dominant in thin oxides of thicknesses less than 12 nm. Storage of the charge on the floating gate allows the threshold voltage (VT) to be electrically altered between a low and a high value to represent logic 0 and 1, respectively.
In floating gate memory devices, charge or data is stored in the floating gate and is retained when the power is removed. All floating gate memories have the same generic cell structure. They consist of a stacked gate MOS transistor as shown in figure 1. The first gate is the floating gate that is buried within the gate oxide and the inter-polysilicon dielectric (IPD) beneath the control gate. The IPD isolates the floating gate and can be oxide or oxide-nitride-oxide, ONO. The SiO2 dielectric surrounding the transistor serves as a protective layer from scratches and defects. The second gate is the control gate which is the external gate of the memory transistor. Floating gate devices are typically used in EPROM (Electrically Programmable Read Only Memory) and EEPROM's (Electrically Erasable and Programmable Read Only Memory).
Figure 1. A typical floating gate memory
Charge-trapping devices were invented in 1967  and were the first electrically alterable semiconductor devices. In charge-trapping memory devices, charge or data is stored in the discrete nitride traps and is also retained when the power is removed. Charge-trapping devices are typically used in MNOS (Metal Nitride Oxide Silicon) , , SNOS (Silicon Nitride Oxide Semiconductor) , and SONOS (Silicon Oxide Nitride Oxide Semiconductor) . Figure 2 shows a typical MNOS charge-trapping memory structure.
Figure 2. An MNOS memory cell structure.
The charges in MNOS memories are injected from the channel region into the nitride by
quantum mechanical tunneling through an ultra-thin oxide (UTO) which is typically 1.5
- 3 nm.
The first EPROM, a floating gate device, was developed using a heavily doped polysilicon (poly-Si) as the floating gate material known as the floating gate avalanche-injection MOS memory (FAMOS) . The gate oxide thickness was of the order of 100 nm to prevent weak spot or shorting path between the floating gate and the substrate. Charging of the EPROM was achieved by biasing the drain junction to avalanche breakdown where the electrons in the avalanche plasma were injected from the drain region into the floating gate. The FAMOS could only be erased by ultraviolet (UV) or x-ray. The EPROM was perceived as a tool for system prototyping before a design was committed to Read Only Memory (ROM). Today, one can obtain EPROM's in either a ceramic package with a quartz window that allows for UV exposure or a plastic package without a quartz window. These memories are known as one-time-programmable (OTP) EPROM's. OTP's are inexpensive, however, additional testing after assembly is not possible. EPROM's in ceramic packages with a quartz window are expensive but do allow additional testing since the memory can be erased using UV light.
Although the 1970's saw the UV-erasable, electrically programmable memories become commercially successful, there was an ever-present attraction toward making the EPROM's electrically erasable, EEPROM. H. Iizuka et. al , proposed the first electrical erasing NVM known as the stacked gate avalanche-injection MOS (SAMOS) memory. SAMOS memory consisted of double poly-Si gates with an external control gate. The external control gate made electrical erasability possible and as a result improved the erasing efficiency. The EEPROM's basic approach with electrical means of restoring the charged floating gate to its original uncharged status replaced UV emission approach. Cheaper packaging and a greater ease of use were the first advantages of EEPROM's over their UV-erasable counterparts. The disadvantage of EEPROM's was the cell size that was two to three times the size of an EPROM cell that resulted in a larger die size. EEPROM cells consist of two transistors, one, a floating gate transistor and the other, a select gate transistor, as shown in figure 3. The select gate transistor is used to select or deselect floating gate transistors for programming or erasing. Die size was further increased to incorporate error correction circuitry or redundancy circuits.
Figure 3. An EEPROM with select gate transistor.
During the 1980's, a novel nonvolatile memory product was introduced, referred to as Flash EEPROM . The first products were merely the result of adapting EPROM's in such a way that the cell could be erased electrically as well. These devices used hot-electron injection for programming and tunneling for erasing. This new genre of Flash EEPROM's could not be erased by bytes but could only be erased by the entire chip or large sections of the chip. Since the need to erase by bytes as in EEPROM's was no longer needed in Flash EEPROM's, the select transistor was removed from the cell structure. Thus the Flash EEPROM's were two to three times smaller than earlier EEPROM cells. The generic cell structure of a Flash EEPROM is similar to a generic cell structure shown in figure 1.
Below is a nomenclature or a list of memory terms (not exhaustive) used in the literature, industry, and education fields:
Figure 4. Energy band diagram of a floating gate
memory during programming by FN tunneling.
In the figure, ec and ev are the conduction and valence bands respectively, Eg is the energy band gap (1.1 eV for silicon), fb is the Si-SiO2 energy barrier (fb is 3.2 eV for electrons and 4.7 eV for holes). The applied Vcg creates the electric field resulting in a potential barrier. This barrier provides a path for the electrons in the substrate to tunnel through the thin gate oxide (typically less than 12 nm) and eventually be collected in the n+ poly-Si floating gate. The bending of the energy bands of the IPD and the gate oxide are different due to the thickness differences between them. The IPD ranges from 25 nm to 45 nm while the gate oxide ranges from 5 nm to 12 nm. The electrons collected at the floating gate leads to a tunneling current density and is given by .
h = Planck's constant
= Energy barrier at the injecting surface (3.2 eV for Si-SiO2)
q = Charge of a single electron (1.6x10-19 C)
m = Mass of a free electron (9.1x10-31 kg)
m* = Effective mass of an electron in the band gap of SiO2 (0.42 m)
?inj = Electric field at the injecting surface = (V/cm)
Vapp = Voltage applied across the tunnel oxide (V)
Vfb = Flat band voltage (V)
tox = Tunnel oxide thickness (cm)
Equation 1 shows that tunneling current density is exponentially dependent on the applied voltage, Vapp, which influences the electric field, ?inj, across the gate oxide.
Figure 5 shows a cross-section of an NVM with electrons tunneling uniformly with Vcg at positive potential while the source (Vs), the drain (Vd), and the substrate (Vsub) are at ground potential.
Figure 5. Uniform tunneling to program Flash
An optional method that can be used to program Flash EEPROM's is given in figure 6 which is called drain-side tunneling. Drain-side tunneling is sometimes preferred over the uniform tunneling due to the programming speed as a result of higher tunneling current density due to smaller injecting area.
Figure 6. Drain-side tunneling to program Flash EEPROM.
IIb. Hot-carrier Injection (HCI)
NVM's can also be programmed by hot-carrier injection. The method of programming is by hot-electron injection for n-type NVM's built on p-substrates and by hot hole injection for p-type NVM's built on n-substrates. Hot-hole injection is very slow due to the hole mass as well as the Si-SiO2 energy barrier of 4.7 eV for holes, which is why all NVM's manufactured today are n-type on p-substrates.
The memory cell is programmed by charging the floating gate via the injection of hot-electrons from the drains pinch-off region. The hot-electrons get their energy from the voltage applied to the drain (Vd) of the memory cell. They are accelerated by the lateral electric field (Elat) along the channel into even higher fields surrounding the drain depletion region. Once these electrons gain sufficient energy they surmount the energy barrier of 3.2 eV between the silicon substrate and the silicon dielectric layer or gate oxide.
With positive Vd and channel voltages, electrons injected into the oxide of an n-channel memory cells return to the substrate unless a high positive Vcg is applied to pull the electrons toward the floating gate. The energy band structure for NVM programming by hot-electron injection is shown in figure 7.
Figure 7. Energy band diagram of a floating gate memory during programming by hot-electron injection.
As the floating gate becomes fully charged, the gate current (Ig) is reduced to almost zero
because the oxide electric field (Eox) (in the beginning of the injection process Eox was
attractive to the electrons) is now repulsive to the electrons. In general, to the first order,
Vcg increases the charge on the floating gate while Vd affects the programming speed.
Figure 8 shows a cross-section of an NVM with hot-electron injection programming. Vcg and Vd are at positive potential of 15 V and 10 V respectively while Vs and Vsub are at ground potential. The p-well is also shown, as it is the process needed to separate n-channel and p-channel MOS transistors from NVM's devices.
Figure 8. Hot-electron injection mechanism for programming in NVM's.
III. BASIC ERASING MECHANISMS
Section II covered the two programming schemes, namely, FN tunneling and hot-electron injection. In order to reprogram an NVM, it first has to be erased. This section will cover the erasing schemes commonly employed in the industry.
The electrons that are injected into the floating gate are trapped by the high gate to oxide
energy barrier of 3.2 eV. Since the potential-energy barrier at the oxide-silicon interface is greater than 3.0 eV, the rate of spontaneous emission of electrons from the oxide over this barrier is negligibly small. The net negative charge which remains on the floating gate shifts the VT to a positive value.
There are two methods of erasing or removing charge:
Figure 9. Energy band diagram of UV erase of an NVM.
IIIb. FN Tunneling
FN tunneling can also be used to erase an NVM. One of the methods is by applying a large negative voltage at the control gate. The energy band structure will be influenced as shown
in figure 10. The applied Vcg creates the electric field resulting in a potential barrier. This barrier provides a path for the electrons to tunnel from the floating gate to the substrate through the thin gate oxide.
Figure 10. Energy band diagram of a floating gate memory during erasing by FN tunneling.
Figure 11a and 11b shows two choices to erase a Flash EEPROM. For uniform tunneling, a large negative Vcg is applied while for drain-side tunneling method, both a negative Vcg and a positive Vd are applied.
Figure 11a. Uniform tunneling to erase Flash EEPROM.
Figure 11b. Drain-side tunneling to erase Flash
In general, uniform tunneling is slower that drain-side tunneling, but, drain-side tunneling tends to cause reliability issues. The reliability issue is the gate oxide damage that occurs near the drain since a small area is bombarded by electrons and that the tunneling current density as a result of small area is higher.
IV. HOT-CARRIER INJECTION MODEL
One of the methods of programming an EPROM or a Flash EEPROM is by channel hot-electron injection (CHE) where hot-electrons are generated in the high field region between the pinched-off channel and drain. Electrons with sufficient energy are injected across the oxide to the floating gate, thereby programming the device (increasing the threshold voltage to positive value, VT). This process of programming is slow due to the injection efficiency, which is dependent on three probability events. The hot-carrier injection mechanism gives rise to impact ionization at the drain, by which both minority (electrons) and majority (holes) carriers are generated. The highly energetic holes are normally collected at the substrate contact and form the substrate current (Isub) while the minority carriers are collected at the drain and forms the drain current (Ids). If the oxide electric field (Eox) favors injection, these carriers are injected over the energy barrier (fb) of the gate oxide and gives rise to hot-carrier injection gate current (Ig). In the case of floating gate memories, these electrons change the charge content of the floating gate.
There are two models that can be used to describe the gate current due to hot-electron injection. The two models are the lucky-electron model  and the effective electron temperature model .
IVa. Lucky-electron Model and Threshold Programmed VT
The lucky-electron approach of modeling the hot-electron distribution was originated by Shockley . Conceptually, the lucky-electron model can be described as follows. In order for hot-electrons to reach the gate, the hot-electrons must gain sufficient kinetic energy from the lateral channel field (Elat) and have its momentum redirected towards the Si-SiO2 interface in order to surmount the SiO2 energy barrier (fb). Figure 12 shows the concepts involved in the lucky-electron model. The three events involved in the lucky-electron model are:
Figure 12. The three processes in the
lucky-electron injection model.
DVT = VT (Programmed) - VT (Initial)
DQfg = Qfg (Programmed) - Qfg (Initial) = Change in floating gate charge.
The floating gate charge changes according to
Dt is the programming time (s)
The change in floating gate charge shifts VT from the initial or natural threshold voltage VTi by
Cfg = Floating gate to control gate capacitance (F)
Figure 13 shows a typical transfer characteristic for the programmed and initial or erased states. The figure shows that the Ids-Vcg curves are parallel to each other. The shift of the Ids-Vcg curve from initial or erased state to programmed state is equal to DQfg/ Cfg.
Figure 13. Ids-Vcg transfer characteristics.
V. NONVOLATILE MEMORY RELIABILITY
Nonvolatile memory cells have some important functional characteristics, which are used to evaluate the performance of the cell. These characteristics are divided into two main classes, namely endurance and retention. In order to understand endurance and retention characteristics, it is imperative to know some of the fundamentals associated with gate oxide and interpolysilicon dielectric, IPD, integrity. Although traps are the storage sites in MNOS, SNOS, and SONOS memories, they constitute the very means that lead to reliability failures in EPROM's, EEPROM's, and Flash EEPROM's. The gate oxide and IPD quality can affect endurance and retention.
The primary failure mechanism of the gate oxide pertains to oxide breakdown and trap-up due to high injection electric field stressing during hot-electron injection or FN tunneling. It was suggested that oxide defects and broken Si-O bonds serve as trapping centers  for positive (holes) charge. Oxide breakdown occurs after a fixed amount of charge per unit area (Qbd) has been injected and has been shown to be a function of applied electric field . Qbd is an industry standard electrical test used to measure the quality of the oxide with higher Qbd (good oxide quality) as the desired goal. Trap-up is defined as the trapping of electrons in the oxide during programming/writing operations. These trapped charges change the injection fields and thus, the amount of charge transferred to and from the floating gate during programming.
As described earlier, one of the components of a nonvolatile memory cell structure is the IPD. In nonvolatile memories, IPD is used to isolate the floating gate from other electrodes (control gate, source, drain, and the substrate) and hence, should be defect-free to prevent charge leakage from the floating gate. Since the floating gate is a poly-Si layer, it is commonly oxidized during the IPD growth process. The oxidation of poly-Si layer modifies the surface topology due to enhanced oxidation at the grain boundaries of the poly-Si, forming interface protuberances and inclusions . The surface nonuniformities causes electric field enhancement resulting in higher leakage currents, which is a drawback for an insulating IPD. Figure 14 shows a circuit diagram of the effects of nonuniformities with respect to electric field enhancement. Other factors that influences the IPD quality are the doping of the floating gate poly-Si layer and the temperature of both the poly-Si deposition and the oxidation . Multiple dielectric stacks such as the oxide-nitride-oxide (ONO) are now commonly used as IPD's for lower leakage due to lower defect densities and higher electric field properties . The lower leakage currents are achieved due to the fact that the electrons that have leaked from the floating gate gets trapped in the oxide-nitride interface which builds an electric field that opposes further charge loss . Typical thicknesses of the ONO stack are 5 - 10 nm, 20 nm, and 3 nm for the bottom oxide, nitride, and the top oxide respectively. The bottom oxide is the oxide above the floating gate while the top oxide is the oxide beneath the control gate.
Figure 14. IPD leakage current due to
Va. Endurance Characteristics
The endurance characteristics give the memory threshold voltage window, which is the difference between the threshold voltages in the programmed/written state and the erased states, as a function of the number of programming cycles, as shown in figure 15. Nonvolatile memories can be programmed and erased frequently at the expense of introducing permanent gate oxide damage such as oxide breakdown and trap-up. This implies that the total number of program operations is limited; for example, most commercially available EEPROM products are guaranteed to withstand 106 programming cycles. The damaging of the memory cell during cycling is normally referred to as "degradation" and the number of cycles the memory can withstand is called "endurance". Threshold voltage window closure occurs when the threshold voltage difference between the programmed and erased states cannot be distinguished. The phenomenon of window closure has been attributed to trapping of injected electrons in the gate oxide due to pre-existing electron traps. There is also evidence of trap generation during programming and erasing due to high electric field stress (Einj). It is thus important to have high quality gate oxides that can endure constant electron stress during hot-electron injection or FN tunneling.
Figure 15. Typical EEPROM cell threshold voltage window versus log cycles.
Vb. Retention Characteristics
When a nonvolatile memory cell can no longer hold the charge in
the floating gate, it is said to have affected its retention
capability. Retention is a measure of the time that a nonvolatile
memory cell can retain the charge whether it is powered or
unpowered. In floating gate memories, the stored charge can leak
away from the floating gate through the gate oxide or through the
IPD. This leakage caused by mobile ions and oxide defects, result
in a shift of the threshold voltage of the memory cell. Different
charge loss mechanisms have been described , , namely,
charge loss due to thermionic emission, charge loss due to electron
detrapping, and charge loss due to contamination such as positive
mobile ions. To improve the retention characteristics of the memory
cell, various improvements to the quality of the gate oxide and IPD
becomes very important.
Retention can be quantified by measuring or estimating the time it takes for the floating gate to discharge when it is intended to keep the information stored. When charge loss occurs, a shift in the VT of the memory cell occurs according to equation 8.
where dQFG, CFG, and dVT are the floating gate charge loss, floating gate capacitance, and the floating gate VT shift respectively. Equation 9 shows the evaluation of the number of electrons lost and equation 10 shows how the number of electrons lost is related to leakage current, ILeakage and retention time, dt.
For a typical CFG of 30 fF and a VT shift of 3 V, the # of electrons lost from the floating gate to control gate is 5.6x105. Table 1 shows the retention time, dt, for various ILeakage associated with a loss of 5.6x105 electrons or 3 V VT shift.
Leakage Current, ILeakage (A)
Retention Time, dt (Years)
Table 1. Retention time as function of
Table 1 shows that it would take 10 years for an NVM to loose charge equivalent to 3 V shift for a leakage current of 2.85x10-22 A.
Vc. Memory Disturbs
Widespread use of nonvolatile memories in production systems requires data retention
for ten years or more. A typical memory array undergoes stresses that arise during programming and erasing commonly referred to as disturbs. The four principal memory cell disturbs that can occur in an array are dc erase, dc program, program disturb, and read disturb . The two common disturbs that can impact memory cells during programming are dc program and program disturb. Memory cell disturbs can also occur during erasing and is called dc erase. Finally, during "read" operation when the memory is read to determine the state (logic 0 or 1), memory cell disturb can also occur and is called read disturb. Figure 16 shows the schematic description of a memory array and will be used to describe the memory cell disturbs.
Figure 16. Schematic description of a memory array with disturbs.
In figure 16, the memory array has columns connected to the drain of each memory cell
(COL 1, COL 2, and COL 3) that represent the "bitline" and are used to select or deselect the memory cell for programming or erasing. The memory array also has rows that are connected to the control gate of each memory cell (ROW 0 and ROW 1) that represent the "wordline" and are also used to select or deselect the memory cell for programming or erasing. From previous discussions on hot-carrier injection, both the bitline and the wordline have to have voltages applied in order for the memory cell to program. If either the bitline or the wordline is not connected to a high potential, then hot-carrier injection will not occur.
The four types of memory disturbs are:
1) DC Erase: This type of disturb occurs on cells that are already programmed (Cell A). These programmed cells are on the same wordline (ROW 1) as the cell being programmed (COL 2 and ROW 1). During the programming operation ROW 1 is brought to a high voltage of 15 V. The electric field due to the high voltage appears across the IPD, which may be high enough to cause conduction of electrons across it from the floating gate (also known as poly-Si to poly-Si erase mode mechanism) to the control gate. The result, loss of charge and consequent reduction of the programmed threshold voltage, which in severe cases causes complete loss of data.
2) DC Program: Also known as gate-disturb, occurs on cells that are unprogrammed or in erased state (Cell B). These unprogrammed cells are on the same wordline (ROW 1) as the cell being programmed (COL 2 and ROW 1). These unprogrammed cells have a few electrons on their floating gates and thus low threshold voltages, VT. When ROW 1 is raised to 15 V, the electric field across the tunneling gate dielectric may be high enough to cause electron tunneling into the floating gate from the substrate and increase the VT. In severe cases, the cell is programmed unintentionally and is called soft-write.
3) Program Disturb: Also known as drain-disturb occurs on programmed cells. A programmed cell (Cell C) sharing a column (COL 2) with the cell being programmed (COL 2 and ROW 1) will also experience high electric fields between the floating gate and the drain. This may cause electrons to tunnel from the floating gate to the drain, and lead to a reduced VT.
4) Read Disturb: This disturb mechanism occurs on erased bits that share a wordline with a bit that is being read. The common wordline places the control gate of the erased cells at 5 V. The selected device's drain is driven to about 1 V. The unselected bits have their source, drain, and substrate at 0 V.
An NVM overview was given which began with a brief background of nonvolatile memories and the terminology's used in the NVM industry. The two common methods of programming are the hot-carrier injection and FN tunneling. In FN tunneling, gate oxides thicknesses have to be less than 12 nm whereas in the case of hot-carrier injection, the thickness of the gate oxide is not critical. The two common methods employed for erasing are by UV emission and FN tunneling. UV emission is commonly used for UV EPROM's while FN tunneling is commonly employed in EEPROM's and Flash EEPROM's, provided the thicknesses are less than 12 nm. UV emission takes a long time to erase relative to FN tunneling. Typical UV emission erase time is 10 minutes while the FN tunneling takes anywhere from 1 ms to 10 ms depending on the applied potentials at the control gate and the drain. The fastest method of programming is via hot-carrier injection that can typically take up to 100 ms. To understand the physics of hot-carrier injection, a "lucky-electron" model was covered. The model shows how the gate current is evaluated based on various probability events. Although the injection efficiency is low, the process of adding electrons onto the floating gate is fast due to high electric fields. As for every device, reliability issues are encountered. Endurance and data retention are the two common reliability issues an NVM undergoes. In addition to endurance and data retention, memory disturbs also occur due to memory stressing during programming and erasing.
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